The disclosure herein relates generally to semiconductor processing, and more particularly to fashioning a lateral bipolar transistor having one or more compensated well regions.
Several trends presently exist in the semiconductor and electronics industry. Devices are continually being made smaller, faster and requiring less power. One reason for these trends is that more personal devices are being fabricated that are relatively small and portable, thereby relying on a battery as their primary supply. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of these trends, there is an ever increasing demand in the industry for smaller and faster transistors used to provide the core functionality of the integrated circuits used in these devices.
Accordingly, in the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. To achieve high densities, there have been and continue to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers, that are generally produced from bulk silicon. In order to accomplish such high densities, smaller feature sizes, smaller separations between features, and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges).
It can be appreciated that significant resources go into scaling down device dimensions and increasing packing densities. For example, significant man hours may be required to design such scaled down devices, equipment necessary to produce such devices may be expensive and/or processes related to producing such devices may have to be very tightly controlled and/or be operated under very specific conditions, etc. Accordingly, it can be appreciated that there can be significant costs associated with exercising quality control over semiconductor fabrication, including, among other things, costs associated with discarding defective units, and thus wasting raw materials and/or man hours, as well as other resources, for example. Additionally, since the units are more tightly packed on the wafer, more units are lost when some or all of a wafer is defective and thus has to be discarded. Accordingly, techniques that mitigate yield loss (e.g., a reduction in the number of acceptable or usable units), among other things, would be desirable.